While Moore’s Law relentlessly progresses, chip designers are constantly challenged to increasing chip complexity in terms of multi-million gate counts and process geometries shrink. The bottom line is that the design and implementation of sub-130 nanometer chips poses a challenge on how we move back-end critical decisions-making up front. With MyMeth, our experienced consultants can help you make that critical decisions in order to meet tough project deadlines.

MyMeth specializes in both hierarchical and flat methodology which covers both physical and timing convergence aspects of sub-130 nanometer design and verification: design partitioning for floorplanning and placement; workable methodology for clock-tree synthesis; congestion analysis and prevention; sub-microns process geometry effects.